SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. ASIC SOC STA ENGINEER (STARLINK)
Would you like to become part of team developing silicon for Starlink’s low earth orbit satellites that deliver broadband connectivity to the people who either do not have access to internet or have spotty connectivity? Come join the team working on silicon projects that are driving more integration, lower power, mixed signal architectures and next generation silicon technology for deployment in space and ground infrastructures.
- Ownership of full chip and block level timing closure throughout the entire project cycle (RTL, synthesis and physical implementation)
- Develop synthesis scripts and work with design team to evaluate different approaches and devise the best method to synthesize blocks
- Drive and define timing signoff criterion, methodology, constraints, and constraint sign-off and structural checks impacting timing
- Generate block and full chip timing constraints
- Work with physical design team to close and sign-off on timing
- Bachelor’s degree in electrical engineering, computer engineering or computer science
- 5+ years of experience working with ASICs
- Experience with synthesis, STA tools and flow
PREFERRED SKILLS AND EXPERIENCE:
- Experience solving complex problems including clock domain crossings and power optimization
- Experience with ASIC design flow, methodologies, physical design and verification
- Knowledge of timing corners/modes, process variations and signal integrity related issues
- Familiar with advanced silicon process and technology nodes for high speed and low power consumption
- Experience in writing ASIC timing constraints and timing closure
- Experience with high reliability design and implementations
- Strong scripting skills (csh/bash, Perl, Python, etc.)
- Familiar with implementation or integration of design blocks using Verilog/System Verilog
- Ability to work in a dynamic environment with changing needs and requirements
- Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
- Enjoys being challenged and learning new skills
- Must be willing to travel when needed (typically <10%)
- Willing to work extended hours and weekends as needed
- This position can be based in either Redmond, WA or Irvine, CA
- To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.
Location/Region: Irvine, CA